As electronic components are getting smaller and smaller, along with the internal structures in integrated circuits, it is getting easier to either completely destroy or otherwise impair electronic components. In particular, many integrated circuits are highly susceptible to damage from the discharge of static electricity. Generally, electrostatic discharge (ESD) is the transfer of an electrostatic charge between bodies at different electrostatic potentials or voltages, caused by direct contact or induced by an electrostatic field. The discharge of static electricity, or ESD, has become a critical problem for the electronics industry.
Device failure resulting from ESD events are not always immediately catastrophic or apparent. Often the device is only slightly weakened, but is less able to withstand normal operating stresses. Such a weakened device may result in reliability problems. Therefore, various ESD protection circuits should be included in an integrated circuit to protect its various components.
When an ESD pulse occurs on a transistor, the extremely high voltage of the ESD pulse can break down the transistor and can potentially cause permanent damage. Consequently, the circuits associated with the input/output pads of an integrated circuit need to be protected from ESD pulses to prevent such damage.
Integrated circuits, and the geometry of the transistors that make up the integrated circuits, continue to be reduced in size and the transistors are arranged closer together. A transistor's physical size limits the voltage that the transistor can withstand without being damaged. Thus, breakdown voltages of transistors are lowered and currents capable of overheating components are more frequently reached by the voltages and currents induced by an ESD event.
In order to remedy problems with lower device yields stemming from ESD events, the semiconductor industry has recommended a number of different ESD event models to be used for ESD test criteria and design goals. One of these ESD event models, the charged device model (CDM), models rapid ESD events likely to occur during the semiconductor manufacturing and handling process. The ESD events modeled by CDM represent instantaneous discharge. Such an ESD event may consist of a peak current a few Amps and may last for about 1 ns with a rise time of about 200 ps.
Designing an ESD device for CDM events is challenging because most ESD devices show a rise-time dependent turn-on behavior. This behavior leads to voltage overshoots as long as the ESD device is not fully triggered. These voltage overshoots are especially pronounced for pulses with short rise-times and may destroy e.g. gate oxides connected to the node to be protected. This problem becomes especially critical for specific pads where, due to performance reasons, thin gate oxides have to be connected without any secondary ESD protection. Thus, there is a need for ESD protection devices that can be rapidly triggered, yet still conduct large currents.